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tc94a23f 2002-02-06 1 toshiba cmos digital integrated circuit silicon monolithic tc94a23f single-chip cd processor with built-in controller tc94a23f is a single-chip cd processor for digital servo. it incorporates a 4-bit microcontroller. the controller features an lcd/led driver, 4-channel 6-bit ad converter, 2/3-line serial interface, buzzer, interrupt function, and 8-bit timer/counter. the cpu can select one of three crystal oscillator operating clocks (16.9344 mhz, 4.5 mhz, and 75 khz), facilitating interface with the cd processor. the cd processor incorporates sync separation protection and interpolation, efm decoder, error correction, digital equalizer for servo, and servo controller. the cd processor also incorporates a 1-bit da converter. in combination with rf amp ta2153fn or ta2109f, tc94a23f can very simply configure an adjustment-free cd player. thus, the ic is suitable for cd systems for automobiles and radio-cassette players. features single-chip cd processor with built-in cmos lce/led driver and 4-bit microcontroller operating voltage: at cd on: v dd = 4.5 to 5.5 v (typ. 5.0 v) at cd off: v dd = 3.0 to 5.5 v (only cpu on) current dissipation: at cd on: i dd = 50 ma (typ.) at cd off: i dd = 2 ma (with 4.5 mhz crystal oscillator, only cpu on) at cd off: i dd = 0.3 ma (with 75 khz crystal oscillator, only cpu on) operating temperature range: ta = 40~85c package: qfp100-p-1420-0.65a (0.65-mm pitch, 2.7-mm thick) one-time prom version: tc94ap09f weight: 1.6 g (typ.)
tc94a23f 2002-02-06 2 4-bit microcontroller program memory (rom): 16-bit 8k-step data memory (ram): 4-bit 512-word instruction execution time: 1.89/1.78/40 s (all one-word instructions) crystal oscillator frequency: 16.9344 mhz/4.5 mhz/75 khz stack level: 8 ad converter: 6-bit 4-channel lcd driver: 1/4 duty, 1/2 or 1/3 bias method, 72 segments max led driver: 4-digit 14-segment (max), also used as lcd driver switched by software i/o port: cmos i/o port: 16 n-channel open drain i/o port: 4 (max) output-only port: 4 (max), also used as cd processor pins input-only port: 4 timer/counter: 8 bit (intr, instruction cycle, 100/1 khz selectable as timer clock) 10, 100, or 500 hz: internal port 2 hz: flip-flop port serial interface: supports 2/3-line method (data length: 4 or 8 bits) buzzer: four types: 0.75, 1, 1.5, and 3 khz four modes: continuous, single-shot, 10 hz intermittent, and 10 hz intermittent at 1 hz interval) interrupt: 1 external, 3 internal (cd sub-sync, serial interface, 8-bit timer) back-up mode: three types clock stop (crystal oscillator off) hardware wait (crystal oscillator on but cpu in operation) software wait (cpu in intermittent operation) reset function: power-on reset, built-in supply voltage detector (detection voltage 2.5 v typ.) cd processor reliable sync pattern detection, sync signal protection and interpolation built-in efm decoder and sub code decoder high-correction capability using cross interleave read solomon code (circ) logical equation c1 correction: dual c2 correction: quadruple supports variable speeds. jitter absorption capability of 6 frames built-in 16 kb ram built-in digital output circuit built-in l/r independent digital attenuators bilingual audio output (note) sub code q data are read-timing free and can be output in sync with audio data. (note) built-in data slice and analog pll (adjustment-free vco used) circuit auto adjustment of loop gain, offset, and balance at focus servo and tracking servo rf gain auto adjustment circuit built-in digital equalizer for phase compensation supports different pickups using built-in digital equalizer coefficient ram. built-in focus and tracking servo control circuit search control supports all modes and realizes high-speed, stable search. lens kick and feed kick use speed control method. built-in afc circuit and apc circuit for disc motor clv servo. built-in defect/shock detector built-in 8 times oversampling digital filter and 1-bit da converter. note: output pins for sub code q data and audio data are also used as lcd driver pins. the function of the pins can be switched by program.
tc94a23f 2002-02-06 3 pin connections note: symbols used for the pins above indicate the following pin functions. note: when the cd is off, the power supply pins for the controller (mv dd ) and the power pins supply for the cd oscillator (xv dd ) are on and the cd processor-dedicated power supply pins (indicated by asterisk * ) are off. 3 m * a r m : cd processor-dedicated pin : power supply pin : cd processor tri-state output pin : cd processor analog input/output pin : reference input pin : controller-dedicated pin com2 (ot2) mv dd mv ss mxi mxo intr rst in2/(vpp) testm dv sl lo dv rl dv dd ro dv rr dv sr p2-1 ( hso in ) p2-0 ( emphin ) p4-3 ( sck/scl ) p4-2 ( si0/si1/sda ) tma x pdo p2v ref v ss sbok v dd sbsy dout ot22 ( cofs ) ot21 ( spda ) ot20 ( spck ) testc in1 ( bckin ) p2-3 ( datain ) p2-2 ( lrckin ) lpfn lpfo pv ref av ss slco rfi av dd rfct rfzi rfrp fei sbad tei tezi foo fmo dmo 2v ref sel v dd v ss xv ss xi xo xv dd vcof tro tebc rfgc v ref p3-0 p4-1 (si2) p4-0 (adin4/buzr) p3-3 (adin3) p3-2 (adin2) p3-1 (adin1) p1-3 p1-2 p1-1 p1-0 mv ss mv dd p8-3 (ot18/ipf) p8-2 (ot17/mbov) p8-1 (s16/aout) p8-0 (s15/bck) s14 (ot18/lrck) s13 (ot17/sfsy) s12 (ot16/data) s11 (ot15/clck) s10 (ot14/zdet) s1 (ot5) m m 3 3 3 r 3 3 3 3 r a a a a a a a a a 3 a a 3 a r a a m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m 3 3 r m m m m m m m m m m m m m m m r m r m m m m m m m m m m m m m m * * * * * * * * * * * * * * 81 85 90 95 100 50 45 40 35 31 1 5 10 15 20 25 30 80 75 70 65 60 55 51 * hold com1 (ot1) com4 (ot4) com3 (ot3) s2 (ot6) s3 (ot7) s4 (ot8) s5 (ot9) s6 (ot10) s7 (ot11) s8 (ot12) s9 (ot13) ot19 ( hso ) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * osc power supply to controller controller test input reset input hold input interrupt input cd processor input/output cd test input i/o ports (16) power supply to controller lcd driver/led driver output port (lcd: 4 18 72 segments max, led: 18 segments) t c 9 4 a 2 3 f (qpf100 pin) cd function pins switched cd function p ins switched to g ethe r
tc94a23f 2002-02-06 4 block diagram p3-3 (adin3) rst testm dv sl lo dv rl dv dd ro dv rr dv sr in1 (bckin) in2 p4-3 (sck/scl) p4-2 ( si0/si1/sda ) tma x pdo p2v ref vcof sbok pv ref sbsy dout ot22 ( cofs ) ot21 ( spda ) ot20 ( spck ) testc mv ss mv dd av ss av dd rfci rfzi rfrp fei sbad tei tezi foo fmo dmo 2v ref sel tro tebc rfgc v ref hold p4-0 (adin4/buzr) p3-1 (adin1) p3-2 (adin2) ot19 ( hso ) xv ss xo xi xv dd v dd v ss com1 (ot1) com2 (ot2) com3 (ot3) com4 (ot4) s1 (ot5) p4-1 (si2) s14 (ot18/lrck) s13 (ot17/sfsy) s12 (ot16/data) s11 (ot15/clck) p8-3 (s18/ipf) p8-2 (s17/mbov) p8-1 (s16/aout) p8-0 (s15/bck) lpfn rfi slco p3-0 intr p2-3 (datain) p2-0 (emphin) p2-1 ( hso in ) p2-2 ( lrckin ) lpfo mxi mxo p1-3 p1-0 s2 (ot6) s10 (ot14/zdet) x?tal osc lpf x?tal osc port1 mpx clock gene. cpu clock timer interrupt cont. port4 buzr ad conv. serial interface port3 lcd driver/output port port8 bias 1 bit dac zdet pwm cd clock v ref sbsy da servo control digital equalizer automatic adjustment circuit rom ram 16 k sram clv servo v ref synchronous guarantee efm decode sub code decoder data slicer v ref pll tmax vco correction circuit address ad digital out audio out micon interface data reg (16 bit) rom (16 8192 step) program counter stack reg. (8level) g-reg. r/w buf. alu ot19-22 port2 power on reset f/f reset zdet, clck, data, sfsy, lrck, bck, mbov, ipf ram (4 512 word) instruction decoder sbsy clck, data, sfsy, lrck, bck, mbov, ipf cd reset p2-0~p2-3 in1 reset
tc94a23f 2002-02-06 5 pin function pin number symbol pin name function and operation remarks 97 com1/ot1 98 com2/ot2 99 com3/ot3 100 com4/ot4 lcd common output /output port common signal output pins for the lcd panel. those pins configure matrix with s1 to s18 and display up to 72 segments. the lcd can be driven by the 1/2 or 1/3 bias method. when the 1/2 bias method is set, three levels, mv dd , 1/2mv dd , and gnd, are output at 2-ms intervals at a 62.5 hz cycle. when the 1/3 bias method is set, four levels, mv dd , 1/3mv dd , 2/3mv dd , and gnd, are output at 1-ms intervals at a 125 hz cycle (when either the 4.5 mhz or 75 khz crystal oscillator is used). after system reset or clock stop execution is released, the non-selected waveform (bias voltage) is output. the disp off bit is set to 0 and the common signal is output. these pins can be switched to an output port (note 1) or led driver pins by program. they are usually used for digit output to drive the leds. mv dd mv dd bias voltage
tc94a23f 2002-02-06 6 pin number symbol pin name function and operation remarks 1~9 s1/ot4 ~ s9/ot13 lcd segment output /output port 10 s10/ot14 /zdet 11 s11/ot15 /clck 12 s12/ot16 /data 13 s13/ot17 /sfsy 14 s14/ot18 /lrck lcd segment output /output port /cd signal 15 p8-0/s15 /bck 16 p8-1/s16 /aout 17 p8-2/s17 /mbov 18 p8-3/s18 /ipf i/o port /lcd segment output /cd signal segment signal output pins for the lcd panel. those pins configure a matrix with com1 to com4 and display up to 72 segments. when the 1/2 bias method is set, two levels, mv dd and gnd, are output. when the 1/3 bias method is set four levels, mv dd , 1/3mv dd , 2/3mv dd , and gnd, are output. the s1 to s14 pins can be switched to an output port (note 1) by program. port 8 and s15 to s18 pins can be switched pin by pin to an i/o port and segment output pins. when the pins are set to an i/o port, output is n-channel open drain. the s10 to s14 and p8-0 to p8-3 pins can be switched to cd signal input/output pins by program. setting the cd10 bit to 1 switches the pins to the lrck, bck, and aout pins as the cd pins in batches. the other pins can be individually switched according to the s14/s15/s16 segment data. clck: inputs/outputs sub code p to w data reading clock. data: outputs sub code p to w data. sfsy: outputs frame sync signal for playback. lrck: outputs channel clock (44.1 khz). when l channel, outputs low. when r channel, outputs high. the polarity can be inverted by command. bck: outputs bit clock (1.4112 mhz). aout: outputs audio data. mbov: outputs buffer-memory-overflow signal. when buffer memory overflows, outputs h. ipf: outputs interpolation pointing flag. if aout output is c2 error detection/correction, outputs high to indicate correction is impossible. zdet: outputs 1-bit dac zero detection flag. pins set as an output port are used for segment output for the led driver. the output port can increment ot1 to ot18 by instruction, facilitating access to data in external ram and rom. (note 1) after a system reset, pins also used as output ports are set to lcd output; pins also used as i/o ports are set to i/o port input. mv dd mv dd bias voltage mv dd mv dd bias voltage input instruction mv dd
tc94a23f 2002-02-06 7 pin number symbol pin name function and operation remarks 21~24 p1-0~p1-3 i/o port 1 4-bit cmos i/o port. input/output can be set for each bit by program. the pins can be set to be pulled-up or pulled-down by program. thus, they can be used as key input pins. when the pins are set to i/o port input, clock stop mode and wait mode can be released, according to the change in input to the pins. 25 p3-0 i/o port 3 26~28 p3-1/adin1 ~ p3-3/adin3 i/o port 3 /a/d analog voltage input 29 p4-0/adin4 /buzr i/o port 4 /a/d analog voltage input/buzzer output 5-bit cmos i/o port. input/output can be set for each bit by program. p3-1 and p4-0 pins are also used as built-in 6-bit 4-channel a/d converter analog input pins. the built-in a/d converter uses successive approximation. the conversion time is 6 instruction cycles (280 s) when the 75 khz crystal oscillator is used; 198 s when the 4.5 mhz crystal oscillator is used; 180 s when the 16.9344 mhz crystal oscillator is used. a/d analog input can be set for each pin by program. the internal power supply (mv dd ) is used as the reference voltage. the p4-0 pin is also used as the buzzer output pin. one of four frequencies: 0.75, 1, 1.5, and 3 khz, can be selected for buzzer output. the buzzer is output at the selected frequency in one of four modes: continuous, single-shot, 10 hz intermittent, and 10 hz intermittent at 1 hz interval. settings for the a/d converter and buzzer, and their control can be performed by program. 33 p2-0/emphin 34 p2-1/ hso in 35 p2-2/lrckin 36 p2-3/datain i/o port 2 /1-bit dac input 37 in1/bckin 89 in2/ (vpp) general-purpose input port/1-bit dac input (vpp input) i/o port 2 is a 4-bit cmos i/o port. in1 and in2 are a 2-bit general-purpose input port. input/output can be set for each bit of i/o port 2 by program. i/o port 2 and the in1 pins can be switched to 1-bit dac input pins by the cd command to support shock-proofing. in this case, the i/o port must be set to input. with the otp version, the in2 pin is also used as the program power supply pin. mv dd mv dd r in1 mv dd mv dd to a/d converte r input instruction mv dd mv dd mv dd
tc94a23f 2002-02-06 8 pin number symbol pin name function and operation remarks 30 p4-1/s12 i/o port 4/serial data input 31 p4-2 /si0/si1/sda /serial data input/output 32 p4-3 /sck/scl /serial clock input/output 3-bit cmos i/o port. input/output can be set for each bit by program. these pins are also used as serial interface (sio) circuit input/output pins. sio is a serial interface supporting 2-line and 3-line methods. starting from the msb or lsb, 4 or 8-bit serial data are output to the so/sda pin, or data on the si1 and si2 pins are input to the device at the clock edge on the sck/scl pin. as the serial operating clock (sck/scl), an internal (450/225/150/75 khz) or external clock can be selected. rising or falling shift can also be selected. the clock and data output can be n-channel open drain. these selections facilitate controlling the lsi and communications between the controllers. when sio interrupts are enabled, an interrupt is generated as soon as execution of the sio completes, and the program jumps to address 4. this is effective for performing serial communications at high speed. all sio inputs incorporate a schmidt circuit. sio and its control can be set by program. 38 testc 88 testm test mode control input input pins for controlling test mode. when the pins are at high level, the device is in test mode; at low level, in normal operation. normally, set the pins to low level or nc (pull-down resistors are incorporated). 39~42 ot19/ hso ot20/spck ot21/spda ot22/cofs output port/cd control signal output 4-bit general-purpose output port. after system reset, the pins are set to a low-level output port. the pins can be switched to cd control output pins by program. setting ot19 to ot22 to 0 switches all four pins to cd control output pins. setting ot19 to ot22 and cdio to 1 enables the pins to be switched as follows according to the segment data contents of the s15 and s16 pins: hso : outputs playback speed mode. normal speed: high double speed: low spck: outputs clock for reading processor status signal (176.4 khz). apck: outputs clock for reading processor status signal. spda: outputs processor status signal. cofs: outputs frame clock for correction (7.35 khz). mv dd mv dd input instruction si0 on mv dd r in2
tc94a23f 2002-02-06 9 pin number symbol pin name function and operation remarks 43 dout digital output in. 44 sbsy sub code block sync output pin. when sub code sync is detected, outputs high at the s1 position. 45 sbok sub code q data crcc result output pin. when the result is ok, outputs high. 46, 75 v dd 47, 76 v ss power supply pins for cd digital block. normally, 5 v is applied. when cd is not used (cd off), the power supply can be set to off except to the controller, enabling only the controller to operate. at this time, 1 must be set in the cdoff bit. if pins from 11 to 18 and 39 to 42 are set as cd control signal input/output pins, setting the cdoff bit to 1 switches all the pins to an output port. 48 p2v ref 2v ref pin for pll block 49 pdo outputs phase error signal between the efm and plck signals. 50 tmax tmax detection result output pin. selected by command bit tmps. longer than the specified cycle: outputs p2v ref . shorter than the specified cycle: outputs low level (v ss ). within the specified cycle: at high impedance 51 lpfn inverted input pin for low-pass filter amp. 52 lpfo output pin for low-pass filter amp. 53 pv ref v ref pin for pll block 54 vcof vco filter pin 55 av ss cd processor control input/output ground pin for analog block v dd v dd mv ss p2v ref pv ref p2v ref vco pv ref av dd lpfn lpfo pv ref vcof
tc94a23f 2002-02-06 10 pin number symbol pin name function and operation remarks 56 slco dac output pin for generating data slice level 57 rfi rf signal input pin 58 av dd power supply pin for analog block 59 rfct rfrp signal center level input pin 60 rfzi rfrp zero-cross signal input pin 61 rfrp rf ripple signal input pin 62 fei focus error signal input pin 63 sbad sub beam addition signal input pin 64 tei tracking error input pin. the pin is read at tracking servo on. 65 tezi tracking error/zero-cross signal input pin 66 foo focus equalizer output pin 67 tro tracking equalizer output pin 68 v ref cd processor control input/output analog reference voltage power supply pin v ref z in1 dac av dd rfi slco av dd rfzi 1 k typ. 32 k typ. rfct av dd rfrp fei sbad tei v ref av dd tezi z in2 1 k typ. 32 k typ. av dd 2v ref av ss r out3
tc94a23f 2002-02-06 11 pin number symbol pin name function and operation remarks 69 rfgc control signal output pin for adjusting rf amplitude. outputs three-level pwm signal (pwm carrier 88.2 khz). 70 tebc tracking balance control signal output pin. outputs three-level pwm signal (pwm carrier 88.2 khz). 71 fmo focus equalizer output pin. outputs three-level pwm signal (pwm carrier 88.2 khz). 72 dmo disc equalizer output pin. outputs three-level pwm signal (pwm carrier 88.2 khz for dsp block). 73 2v ref analog reference voltage power supply pin (2 v ref ) 74 sel cd processor control input/output apc circuit on/off signal output pin. at laser on, high impedance at uhs high; h level output at uhs high. 77 xv ss 80 xv dd power supply pins for cd crystal oscillator. to control the cd processor power supply and the controller power supply individually, connect the mv dd and mv ss pins to the power supply lines used by the v dd and v ss pins. 78 xi 79 xo cd processor crystal oscillator pins cd crystal oscillator input/output pins. connect a 16.9344 mhz crystal oscillator. the clock is used as the cd system clock and controller system clock. after system reset, this clock is supplied as the controller system clock and starts the cpu. the crystal oscillator can be halted by program. if the 4.5 mhz or 75 khz oscillator is selected as the controller system clock, the oscillator is halted by program when the cd processor is off. during execution of the ckstp instruction, oscillation halts. (note) when switching the controller system clock from the controller oscillator to the cd crystal oscillator, make sure that the cd crystal oscillator is in stable state. p2v ref v ref r out3 v dd xv dd xv ss xo r out1 r fxt1 xi
tc94a23f 2002-02-06 12 pin number symbol pin name function and operation remarks 81 dv sr r-channel d/a converter block ground pin 82 ro r-channel data forward rotation output pin 83 dv rr r-channel reference voltage pin 84 dv dd d/a converter block power supply pin 85 dv rl l-channel reference voltage pin 86 lo l-channel data forward rotation output pin 87 dv sl cd processor control input/output l-channel d/a converter block ground pin 90 rst reset input device system reset signal input pin. while the rst is at low level, reset is applied. when the rst is at high level, the cd block is in operation, and the controller program starts from address 0. normally, when 2.7 v or higher voltage is supplied to the mv dd when at 0 v, system reset is applied (power-on reset). fix the pin to high level. 91 hold hold mode control input input pin used to request or release hold state. normally, the pin is used for inputting the cd mode selection signal or battery detection signal. halt states are clock stop mode (crystal oscillator stops oscillation) and wait mode (cpu stops). the modes are entered using the ckstp and wait instructions. by program, clock stop mode can be entered by detection of low level on the hold pin or by forced execution. clock stop mode can be released by detection of high level on the hold pin or change in the hold pin input. executing the ckstp instruction stops the clock generator and the cpu, entering memory backup state. during memory backup state, current dissipation becomes low (1 a or below). the display output and cmos output port automatically become low level. the n-channel open drain output becomes off. regardless of the hold pin input state, wait mode is executed and current dissipation becomes low. crystal oscillator only on or cpu operation suspended can be programmed. when the crystal oscillator only is on, all displays are at low level. the other pins are in hold state. when cpu operation is suspended, all states are held except that the cpu is suspended. wait mode is released by a change of the hold pin input. (note) to use backup mode, turn off the v dd pin (power supply for cd), and enter backup mode. dv dd v ss dv sl /dv sr dv dd ro/lo dv rr /dv rl mv dd mv dd
tc94a23f 2002-02-06 13 pin number symbol pin name function and operation remarks 92 intr external interrupt input external interrupt input pin. when interrupts are enabled and a pulse of 1.11 to 3.33 s or more (13.3 to 40 s when the 75 khz clock is used) is input to this pin, an interrupt is generated and the program jumps to address 1. input logic and rising/falling edge can be individually selected for interrupt inputs. the internal 8-bit timer clock can be selected for interrupt inputs. interrupts can be generated (address 3) by pulse count or the count value. interrupt inputs are schmidt inputs. the pin can be used as an input port for inputs such as remote control signals. 93 mxo 94 mxi crystal oscillator pins for controller crystal oscillator pins for the controller. the oscillator clock is used as a time base for the clock function as well as the system clock for the controller. after system reset, the cpu starts operation using the 16.9344 mhz cd oscillator (connected to the xi and xo pins). the oscillator is switched to the controller oscillator by program. either a 4.5 mhz reference oscillator or a 75 khz oscillator is connected to the mxo and mxi pins. the oscillators are switched by a bit used to select a frequency of 4.5 mhz or 75 khz. the oscillators incorporate a feedback resistor. switching frequencies automatically switches the feedback resistor of the crystal oscillator. 75 khz: rout2 2 k , rfxt2 10 m typ. 4.5 mhz: rout2 2 k , rfxt2 1 m typ. if the operating clock is the cd crystal oscillator, fix the mxi pin to gnd. during execution of the ckstp instruction, oscillation halts. selection and control of crystal oscillators are done by program. (note) when the 75 khz crystal oscillator is used, externally add/connect a 100 k output resistor. 19, 96 mv dd 20, 95 mv ss power supply pins for controller block power supply pins for the controller block. normally, v dd 4.5 to 5.5 v. in backup state (when executing the ckstp instruction), current dissipation becomes low (1 a or below), dropping the power supply voltage to 2.0 v. if 2.7 v or more is applied to these pins when at 0 v, a system reset is applied to the device and the program starts from address 0 (power-on reset). the cd processor incorporates a power supply detector, which detects the power supply voltage of 2.5 v. (note) at power-on reset operation, allow 10 to 100 ms while the device power supply voltage rises. when not using the power supply detector function, set the test port pins (test#0 to 3) to all 1s so that the cd processor enters halt state. setting to halt state reduces current dissipation by 150 a (typ.). mv dd mxo r out2 r fxt2 mxi mv dd mv ss
tc94a23f 2002-02-06 14 maximum ratings (ta 25c, v dd mv dd dv dd av dd , mv dd xv dd ) characteristic symbol rating unit v dd power supply voltage mv dd 0.3~6.0 (mv dd
v dd ) v (v dd power supply pin) v in1 0.3~v dd 0.3 input voltage (mv dd power supply pin) v in2 0.3~mv dd 0.3 v power dissipation p d 1400 mw operating temperature t opr 40~85 c storage temperature t stg 65~150 c
tc94a23f 2002-02-06 15 electrical characteristics (unless otherwise specified, ta 25c, v dd mv dd xv dd dv dd av dd 5 v, 2v ref p2v ref 4.2 v, v ref pv ref 2.1 v) v dd (power supply pins for cd processor block: v dd , xv dd , dv dd , av dd ) characteristic symbol test circuit test condition min typ. max unit operating power supply voltage range v dd mv dd xv dd
v dd dv dd av dd * 4.5 ~ 5.5 v i dd (v dd , dv dd , av dd ) operating at 16.9344 mhz 50 60 operating power supply current xi dd (xv dd ) 16.9344 mhz crystal oscillator connected 2.0 ma crystal oscillator standby current x stby (xv dd ) 16.9344 mhz crystal oscillator off 0.01 a crystal oscillator frequency f xt c i c o 15 pf (note 1) * 16.9344 mhz mv dd (power supply pins for cpu block: mv dd , xv dd ) (note 2) characteristic symbol test circuit test condition min typ. max unit mv dd1 cpu and cd in operation mv dd xv dd
v dd dv dd av dd * 4.5 ~ 5.5 mv dd2 cpu in operation (cd off, 4.5 mhz /16.9344 mhz crystal oscillator used) * 4.5 ~ 5.5 operating power supply voltage range mv dd3 cpu in operation (cd off, 75 khz crystal oscillator used) * 3.0 ~ 5.5 memory hold voltage range mv hd crystal oscillator stopped (executing ckstp instruction) * 2.0 ~ 5.5 v mi dd1 xi 16.9344 mhz crystal oscillator connected 3.0 5.0 mi dd2 mxi 4.5 mhz crystal oscillator connected 1.4 2.5 mi dd3 cpu in operation mxi 75 khz crystal oscillator connected 0.3 1.0 mi dd4 xi 16.9344 mhz crystal oscillator connected 1.5 mi dd5 mxi 4.5 mhz crystal oscillator connected 0.25 operating power supply current (note 3) mi dd6 standby mode (crystal oscillator only in operation) mxi 75 khz crystal oscillator connected 0.1 ma memory hold current mi hd crystal oscillator stopped (executing ckstp instruction) 0.1 1.0 a f mxt1 4.5 mhz crystal oscillator set (note 1) * 4.5 mhz crystal oscillator frequency f mxt2 75 khz crystal oscillator set, mv dd 2.7~5.5 v (note 1) * 75 khz crystal oscillator start time t st crystal oscillator f mxt 75 khz 1.0 s note 1: design and set constants according to the crystal oscillator to be connected. note 2: the power supply/memory hold current is the value obtained by summing the xv dd and mv dd pin currents. note 3: the values are those when the power supply detector function is operating. setting the function reduces current dissipation by 150 a (typ.). (except in standby mode) an asterisk ( * ) indicates the values are guaranteed when v dd mv dd xv dd dv dd av dd 4.5 to 5.5 v, and ta 40 to 85 c.
tc94a23f 2002-02-06 16 lcd common output/output port (com1/ot1 to com4/ot4) characteristic symbol test circuit test condition min typ. max unit i oh1 v oh 4.5 v (lcd output) 200 600 a high level i oh2 v oh 4.5 v (ot output) 15 30 ma i ol1 v ol 0.5 v (lcd output) 200 600 a output current low level i ol5 v ol 0.5 v (ot output) 4.0 10 ma 1/2 level v bs2 no load (lcd output, 1/2 bias method set) 2.3 2.5 2.7 1/3 level v bs1 1.47 1.67 1.87 bias voltage 2/3 level v bs3 no load (lcd output, 1/3 bias method set) 3.13 3.33 3.53 v segment output, output ports, i/o ports, and cd function output (s1/ot4 to s9/ot13, s10/ot14/zdet to s14/ot18/lrck, p8-0/s14/bck to p8-3/s18/ipf, ot19) characteristic symbol test circuit test condition min typ. max unit i oh1 v oh 4.5 v (lcd output) 200 600 a high level i oh4 v oh 4.5 v (ot output, cd output, excluding p8-0 to p8-3 pins) 1.5 4.0 ma i ol1 v ol 0.5 v (lcd output) 200 600 a output current low level i ol5 v ol 0.5 v (ot output, cd output) 4.0 10 ma input leakage current i li v ih 5.0 v, v il 0 v (p8-0~p8-3) 1.0 a high level v ih (p8-0~p8-3, clck) mv dd 0.8 ~ mv dd input voltage low level v il (p8-0~p8-3, clck) 0 ~ mv dd 0.2 v 1/3 level v bs1 1.47 1.67 1.87 bias voltage 1/2 level v bs3 no load (lcd output, 1/3 bias method set) 3.13 3.33 3.53 v i/o port (p1-0~p4-3) characteristic symbol test circuit test condition min typ. max unit high level i oh3 v oh 4.5 v 0.8 2.0 i ol3 v ol 0.5 v (excluding p4-1, p4-2, p4-3 pins) 1.0 3.0 output current low level i ol5 v ol 0.5 v (p4-1, p4-2, p4-3 pins) 4.0 10 ma input leakage current i li v ih 5.0 v, v il 0 v 1.0 a high level v ih mv dd 0.8 ~ mv dd input voltage low level v il 0 ~ mv dd 0.2 v input pull-up/down resistance r in1 (p1-0 to p1-3 pins) pull-down/up set 25 50 120 k hold , intr input port, rst rst input, 1-bit dac data input (emphin/ hso in/lrckin/datain/bckin) input port (in1/in2) characteristic symbol test circuit test condition min typ. max unit input leakage current i li v ih 5.0 v, v il 0 v 1.0 a high level v ih mv dd 0.8 ~ mv dd input voltage low level v il 0 ~ mv dd 0.2 v
tc94a23f 2002-02-06 17 a/d converter (adin1 to adin4) characteristic symbol test circuit test condition min typ. max unit analog input voltage range v ad adin1~adin4 0 ~ mv dd v resolution vres 6 bit total conversion error 0.5 1.0 lsb analog input leakage i li v ih 5.0 v, v il 0 v (adin1~adin4) 1.0 a dout, sbsy, sbok, sel, ot19/ hso , ot20/spck, ot21/spda, ot22/cofs output characteristic symbol test circuit test condition min typ. max unit high level i oh4 v oh 4.5 v 1.5 4.0 output current low level i ol4 v ol 0.5 v 1.5 4.0 ma pdo, tmax, rfgc, tebc, fmo, dmo, tro, foo output characteristic symbol test circuit test condition min typ. max unit high level i oh6 v oh 3.8 v, p2v ref 4.2 v (pdo, tmax) 2.0 output current low level i ol4 v ol 0.5 v, p2v ref 4.2 v (pdo, tmax) 6.0 ma output resistance r out3 (rfgc, tebc, fmo, dmo, tro, foo) 3.3 k v ref output voltage v oref (rfgc, tebc, fmo, dmo, pdd) v ref pv ref 2.1 v 2.1 v transfer delay time (aout, spda, data, sbsy, sbok) characteristic symbol test circuit test condition min typ. max unit high level t plh 10 transfer delay time low level t phl 10 ns 1-bit da converter characteristic symbol test circuit test condition min typ. max unit total harmony distortion thd n 1 khz sine wave, full-scale input 85 78 s/n ratio s/n 90 98 dynamic range dr 1 khz sine wave, based on 60db input 85 90 crosstalk ct 1 khz sine wave, full-scale input 90 85 db analog output level dac out 1 khz sine wave, full-scale input 1200 1250 1300 mvrms
tc94a23f 2002-02-06 18 others characteristic symbol test circuit test condition min typ. max unit input pull-down resistance r in2 (testc, testm) 10 k xi amp feedback resistance r fxt1 (xi-xo) 1.0 2.0 4.0 m xo output resistance r out1 (xo) 0.5 k when 4.5 mhz crystal set, (mxi-mxo) 0.5 1.0 2.5 mxi amp feedback resistance r fxt2 when 75 khz crystal set, (mxi-mxo) 10 m mxo output resistance r out2 (mxo) 2.0 k 10 5.0 2.5 z in1 set resistance by (rfi) cd command 1.25 input resistance z in2 (tezi) 10 k
tc94a23f 2002-02-06 19 package dimensions weight: 1.6 g (typ.)
tc94a23f 2002-02-06 20 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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